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| 242621 | 85169690422 |
Piotr Patronik, Stanisław J Piestrak*
Design of reverse converters for the general RNS 3-moduli set {2k, 2n − 1, 2n + 1}. EURASIP Journal on Advances in Signal Processing 2023 vol. 2023, art. 92, s. 1-28.
| 2023 | |
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2
| 241341 | 85104856215 |
Mikhail Babenko*, Stanisław J Piestrak*, Nikolay Chervyakov*, Maxim Deryabin*
The study of monotonic core functions and their use to build RNS number comparators. Electronics 2021 vol. 10, nr 9, art. 1041, s. 1-14.
| 2021 | |
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3
| 228820 | 85094210259 |
Mikhail Babenko*, Maxim Deryabin*, Stanisław J Piestrak*, Piotr Patronik, Nikolay Chervyakov*, Andrei Tchernykh*, Arutyun Avetisyan*
RNS number comparator based on a modified diagonal function. Electronics 2020 vol. 9, nr 11, art. 1784, s. 1-16.
| 2020 | |
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4
| 210918 | 85015194333 |
Piotr Patronik, Stanisław J Piestrak*
Design of RNS reverse converters with constant shifting to residue datapath channels. Journal of Signal Processing Systems for Signal Image and Video Technology 2018 vol. 90, nr 3, s. 323-339.
| 2018 | |
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5
| 210916 | 85022191883 |
Piotr Patronik, Stanisław J Piestrak*
Design of residue generators with CLA/compressor trees and multi-bit EAC. W: LASCAS 2017 : 8th Latin American Symposium on Circuits and Systems : Bariloche, Argentina, February 20-23, 2017 : R9 IEEE CASS Flagship Conference : proceedings / CAS - IEEE Circuits and Systems Society. [Danvers, MA] : IEEE, cop. 2017. s. 1-4.
| 2017 | |
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6
| 210920 | 85029751226 |
Piotr Patronik, Stanisław J Piestrak*
Design of reverse converters for a new flexible RNS five-moduli set {2k , 2n − 1,2n + 1,2n+1 − 1,2n−1 −1} (n Even). Circuits, Systems, and Signal Processing 2017 vol. 36, nr 11, s. 4593–4614.
| 2017 | |
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7
| 210898 | 85015673904 |
Piotr Patronik, Stanisław J Piestrak*
Hardware/software approach to designing low-power RNS-enhanced arithmetic units. IEEE Transactions on Circuits and Systems. 1, Regular Papers 2017 vol. 64, nr 5, s. 1031-1039.
| 2017 | |
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8
| 206465 | |
Piotr Patronik, Stanisław J Piestrak*
Design of a low-power RNS-enhanced arithmetic unit. W: LASCAS 2016 : VII IEEE Latin American Symposium on Circuits and Systems : R9 IEEE Cass Flagship Conference, February 28 to March 2, 2016 / Pedro Julián, Andreas G. Andreou (eds.). Danvers, MA : IEEE, cop. 2016. s. 151-154.
| 2016 | |
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9
| 241522 | 84946208310 |
B. Chagun Basha*, Sébastien Pillement*, Stanisław J Piestrak*
Fault-aware configurable logic block for reliable reconfigurable FPGAs. W: 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May 24-27, 2015. [Danvers, MA] : IEEE, cop. 2015. s. 2732-2735.
| 2015 | |
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10
| 241342 | 84919665539 |
Stanisław J. Piestrak*
A note on RNS architectures for the implementation of the diagonal function. Information Processing Letters 2015 vol. 115, nr 4, s. 453-457.
| 2015 | |
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